Kintex® UltraScale™ FPGA Datasheet by Xilinx Inc. | Digi-Key Electronics
US7440495B1 - FPGA having AC coupling on I/O pins with an effective bypass of the AC coupling - Google Patents
FPGA Virtex_Spartan | 赛灵思 | 电路设计 | IC合作伙伴 | 爱普生器件
FPGA Virtex_Spartan | 赛灵思 | 电路设计 | IC合作伙伴 | 爱普生器件
Xilinx FPGA LVDS interface with AC coupling/DC biasing termination related question
MGT and GCLK as ref clk?
Does AC coupling capacitors required on MGTRX PCIe transceiver input pins ?
Xilinx FPGA LVDS interface with AC coupling/DC biasing termination related question
Xilinx UG386 Spartan-6 FPGA GTP Transceivers, User Guide
Does AC coupling capacitors required on MGTRX PCIe transceiver input pins ?
Xilinx FPGA LVDS interface with AC coupling/DC biasing termination related question
Gigabit Transceivers - Opal Kelly Documentation Portal
Location of AC coupling capacitors | Forum for Electronics
Location of AC coupling capacitors | Forum for Electronics
FPGA Virtex_Spartan | 赛灵思 | 电路设计 | IC合作伙伴 | 爱普生器件
Beyond Design: AC/DC is Not Just a Rock Band
Broadcast Evaluation Kit Proposal
MGT Reference Clock Input Common Mode Voltage
Does AC coupling capacitors required on MGTRX PCIe transceiver input pins ?
AN-905 Using VersaClock® 6 as Reference Clock for Xilinx® Series 7 FPGAs
AC/DC Coupling Guidelines
FPGA Virtex_Spartan | 赛灵思 | 电路设计 | IC合作伙伴 | 爱普生器件
MGT Channel LVDS Input Clock : 네이버 블로그
High-Speed Digital Logic (HSDL) Interfacing HSDL Current-Mode Logic (CML) to Other I/O Logic Standards
Advantages of AC-Coupling in SerDes Applications
Design of a self-test vehicle for AC coupled interconnect technology
MGTREFCLK levels for an Artix-7
