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![PDF] A 0.38 pj/bit 1.24 nW chip-to-chip serial link for ultra-low power systems | Semantic Scholar](https://d3i71xaburhd42.cloudfront.net/f463cac1fe061c122e275108aaad87f2c4500c5d/3-TableI-1.png "PDF] A 0.38 pj/bit 1.24 nW chip-to-chip serial link for ultra-low power systems | Semantic Scholar")
PDF] A 0.38 pj/bit 1.24 nW chip-to-chip serial link for ultra-low power systems | Semantic Scholar
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Figure 3 from A 0.9 pJ/bit, 12.8 GByte/s WideIO memory interface in a 3D-IC NoC-based MPSoC | Semantic Scholar
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Energy cost, in picojoules (pJ) per 64-bit floating-point operation,... | Download Scientific Diagram
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Figure 1 from 0.16-0.25 pJ/bit, 8 Gb/s Near-Threshold Serial Link Receiver With Super-Harmonic Injection-Locking | Semantic Scholar
Energy cost, in picojoules (pJ) per 64-bit floating-point operation,... | Download Scientific Diagram
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