ROM/RAM
Generating and using ROM
How to use Xilinx Block Memory Generator to generate instruction or data memory? : r/FPGA
CSE 141L - Fa08 - Tutorial: Generating a Memory Module with Xilinx "CORE Generator"
Xilinx ZYNQ - Blog 5 - Advanced eXtensible Interface (AXI) and Using Block RAM - Blog - Path to Programmable - element14 Community
how to use "block mem gen" in vivado IP as an axi mode and stand alone mode ? | Forum for Electronics
Lab 5: Memories: ROMs and BRAMs Internal to the FPGA
ROM/RAM
Running a PicoBlaze microcontroller on the Zedboard | Koheron
MicroZed Chronicles: Block RAM Optimization - Hackster.io
Red Pitaya FPGA Project 5 – High-Bandwidth Averager » Anton Potočnik - research website
CSE 141L - Fa08 - Tutorial: Generating a Memory Module with Xilinx "CORE Generator"
Lesson 103 - Example 70: Block RAM - YouTube
What is the fastest way to save PL data - FPGA - Digilent Forum
Storing Image Data in Block RAM on a Xilinx FPGA – Embedded Thoughts
CSE 141L - Fa08 - Tutorial: Generating a Memory Module with Xilinx "CORE Generator"
Creating a BRAM-based Entity Using Xilinx CORE Generator
How to Initialize BRAM with COE file for Xilinx FPGA – Tips Area
ROM/RAM
Xilinx PG058 Block Memory Generator v8.2, LogiCORE IP Product Guide
How to Initialize BRAM with COE file for Xilinx FPGA – Tips Area
AXI4 FULL based block memory controller and Block memory gen - FPGA - Digilent Forum
Customizing the Block Memory Generator IP
Xilinx XAPP463 Using Block RAM in Spartan-3 Generation FPGAs ...
Adding Coefficient or .coe file to the project in Xilinx-ISE - YouTube
Reading data from the Block memory generator which is stored in the form of .coe file
